Interframe deinterleave switching circuit

ABSTRACT

In processing the transfer of digital voice signals, an interframe deinterleave switching circuit automatically switches the interleaving length without requiring any switching signal from the external unit. The circuit detects a voice synchronizing signal, produces a switching signal when the voice synchronizing signal is not detected, and inputs the switching signal to an interframe deinterleaving circuit (I) so that the interleaving length is automatically switched in synchronism therewith.

TECHNICAL FIELD

The present invention relates to an interframe deinterleave switchingcircuit which is capable of automatically switching an interleavinglength in interframe deinterleaving operation performed in a highdefinition television broadcasting system (MUSE system).

BACKGROUND ART

An interframe deinterleaving circuit is employed as a means fordispersing a burst error in the PCM voice signal of the a highdefinition television broadcast. However, because there is a possibilityof employing different interleaving lengths between a transmissionsystem and a package system and therefore a necessity for theirswitching arises, an interframe deinterleave switching circuit is nowunder consideration.

For this reason, the description will be directed to an example of theforegoing conventional interframe deinterleave switching circuit withreference to the drawings.

FIG. 4 is a block diagram showing a conventional interframe deinterleaveswitching circuit and FIG. 5 shows an example of an interframedeinterleaving circuit. In FIG. 4, 1 denotes an interframedeinterleaving circuit. In FIG. 5, 6 to 10 denote shift registers, 11denotes a selector, 12 denotes a counter, denotes an n-decoding circuit,14 denotes an m-coding circuit, and 15 denotes a selector.

Hereinafter, the description will be directed to the operation of theinterframe deinterleave switching circuit having the foregoingarrangement.

An input signal is passed through n ones of the shift registers 6 to 10,each of which corresponds to one-frame of 1350 clocks of a voice signal.These shift registers thus serve to supply the resulting signals 1₀, 1₁,1₂, 1₃, . . . 1_(n-2), 1_(n-1), 1_(n) including the input signal 1₀.

A counter 12 starts to count at an initial value and sends out theoutput to an n-decode circuit 13. When the n-decode circuit 13 convertsthe output into n, a CLEAR signal f₁ appears. When the m-decode circuit14 converts the output into m (m<n), a CLEAR signal f₂ appears. Then,the selector 15 switches F₁ to f₂ in response to a switching signal fromthe external unit and sends out the output g to the counter 12 forclearing it.

When f₁ is conveyed on the switching signal, the counter 12 repeatscounts of 0 to n. And, the selector 11 serves to sequentially select oneof the input signal 1₀ and those outputs 1₁, 1₂, to 1_(n-1), 1_(n) ofthe shift registers 6 to 10 in response to the output of the counter 12.

The foregoing arrangement, however, has a disadvantage in that it isnecessary to pick up a switching signal for an interleave signal fromthe external unit.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an interframedeinterleave switching circuit which is capable of automaticallyswitching an interleaving length without requiring a switching signalfrom the outside.

To achieve this object, the interframe deinterleave switching circuit ofthe present invention includes a synchronism detecting circuit fordetecting a voice synchronizing signal and a switching signal generatingcircuit for generating a switching signal from the output of thesynchronism detecting circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an interframe deinterleaving circuitaccording to an embodiment of the invention;

FIG. 2 is a circuit diagram showing a concrete switching signalgenerating circuit;

FIG. 3 is a view showing some timings diagrams of the switching signalgenerating circuit;

FIG. 4 is a block diagram showing the conventional interframedeinterleave switching circuit; and

FIG. 5 is a circuit diagram showing a concrete interframe deinterleavingcircuit.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the description will be directed to one embodiment of aninterframe deinterleave switching circuit with reference to thedrawings. FIG. 1 is a block diagram showing an interframe deinterleaveswitching circuit according to the embodiment of the invention, FIG. 2is a circuit diagram showing a concrete circuit of a switching signalgenerating circuit, and FIG. 3 is a view showing some timing drawings.

In FIG. 1, 1 denotes an interframe deinterleaving circuit, 2 denotes asynchronism detecting circuit for detecting a voice synchronizingsignal, 3 denotes a switching signal generating circuit for generating aswitching signal, which serves to switch interleaving length, 4 denotesan inverter circuit for inverting a synchronism detecting signal, and 5denotes a D-latch circuit for generating a switching signal.

The operation of the interframe deinterleave switching circuit havingthe foregoing arrangement will be described with reference to FIGS. 1,2, and 3.

An input signal is supplied to the interframe deinterleaving circuit 1in which the signal is subjected to interframe deinterleaving operationwith an interleaving length m. Next, the resulting output is supplied tothe synchronism detecting circuit 2 in which a voice synchronizingsignal is detected from the output. The synchronism detecting circuit 2serves to supply as a synchronism detecting signal b a HIGH level signalwhen it is detected and a LOW level signal when it is not detected.Next, in the switching signal generating circuit 3, the synchronismdetecting signal b is inverted in the inverter circuit 4 and results inbeing a signal c shown in FIG. 3. In the D-latch circuit 5, an inputclock a is straightforward used to generate a switching signal d whenthe signal c is at HIGH level, that is, the synchronism detectingcircuit 2 cannot detect a voice synchronizing signal. It means that theswitching signal d is changed from LOW to HIGH and thus the interleavinglength is changed to n. When the signal c is at LOW level, that is, thesynchronism detecting circuit 2 can detect a voice synchronizing signal,the D-latch circuit 5 keeps supplying the state of clock a given at thepoint in time when the synchronism detecting signal c is at LOW leveland the switching signal d keeps the state in which voice synchronizingsignal can be detected by the synchronism detecting circuit 2. Theperiod t₁ of the clock a is chosen to meet the following relation with atime t₂ extending from the change of the switching signal d to theenabling time to detect the synchronism:

    t.sub.1 /2>t.sub.2

As mentioned above, the present embodiment provides the synchronismdetecting circuit 2 for detecting a voice synchronizing signal and theswitching signal generating circuit 3 in order to switch the switchingsignal for switching the interleaving length.

INDUSTRIAL APPLICABILITY

According to the present invention, the provision of the synchronismdetecting circuit and the switching signal generating circuit makes itpossible to automatically switch interleaving length without requiring aswitching signal from the external unit.

We claim:
 1. An interframe deinterleave switching circuit comprising:aninterframe deinterleaving circuit for changing an interleaving length; asynchronism detecting circuit for detecting a synchronizing signal froman output of said interframe deinterleaving circuit; and a switchingsignal generating circuit for generating a switching signal for causingsaid interframe deinterleaving circuit to switch an interleaving lengthin response to the output of said synchronism detecting circuit.
 2. Theinterframe deinterleaving switching circuit according to claim 1,wherein two interleaving lengths are provided for the interframedeinterleaving circuit and the switching signal generating circuitconsists of a D-latch circuit and an inverter circuit for passing saidoutput of said synchronism detecting circuit to the gate of said D-latchcircuit.